@lanceslance56
Joined Aug 2026
Problems solved
8
4 puzzles as well
Public circuits
20
0 forks by others
Discussion posts
0
questions and answers
D Flip-Flop (Master-Slave)Two gated D latches with an inverted clock between them, sampling D on a clock edge instead of holding a level.0 forks·Sep
Gated D LatchA single data input D, gated by an enable E, replacing the SR latch's two inputs and removing its forbidden state.0 forks·Sep
SR Latch from NOR GatesTwo cross-coupled NOR gates forming an active-high SR latch, the source-side mirror of the NAND version.0 forks·Sep
SR Latch from NAND GatesTwo cross-coupled NAND gates forming the smallest circuit that stores one bit. Active low: pull S' or R' to 0 to set or reset.0 forks·Sep
2:1 MultiplexerSelects one of two inputs based on a select line, built from an inverter, two AND gates, and an OR gate.0 forks·Sep
Half SubtractorComputes A minus B for two bits, producing a DIFFERENCE and a BORROW.0 forks·Sep
Full AdderAdds two bits plus a carry-in, built from two half adders and an OR gate.0 forks·Sep
Half AdderAdds two single bits and produces a SUM and a CARRY, using one XOR gate and one AND gate.0 forks·Sep
XNOR Gate from NAND GatesA 2-input XNOR gate built from five NAND gates: XOR with an extra inverter on the output.0 forks·Sep
XOR Gate from NOR GatesA 2-input XOR gate built from five NOR gates.0 forks·Sep
NOT Gate from a NOR GateAn inverter built from a single NOR gate with both inputs tied together.0 forks·Sep
OR Gate from NOR GatesA 2-input OR gate built from two NOR gates, cancelling out NOR's own inversion.0 forks·Sep
AND Gate from NOR GatesA 2-input AND gate built from three NOR gates using De Morgan's law.0 forks·Sep
NOR Gate from NAND GatesA 2-input NOR gate built from four NAND gates: an OR construction with an extra inverter.0 forks·Sep
XOR Gate from NAND GatesA 2-input XOR gate built from four NAND gates, the classic minimal construction.0 forks·Sep
NOT Gate from a NAND GateAn inverter built from a single NAND gate with both inputs tied together.0 forks·Sep
OR Gate from NAND GatesA 2-input OR gate built from three NAND gates using De Morgan's law.0 forks·Sep
AND Gate from NAND GatesA 2-input AND gate built from two NAND gates, the smallest possible NAND-only construction.0 forks·Sep
Test Project0 forks·Aug
8-bit ALUtwo 8-bit buses, 3 select lines, the SUB-detect gates, and 8 subcircuit instances of the slice (one per bit), ripple-carry chained, feeding an 8-bit output bus, a COUT flag, and an 8-input NOR ZERO flag.0 forks·Aug