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Contents

Implementation of AND Gate from NAND Gate Implementation of OR Gate from NAND Gate Implementation of NOT Gate from NAND Gate Implementation of XOR Gate from NAND Gate Implementation of NOR Gate from NAND Gate Implementation of AND Gate from NOR Gate Implementation of OR Gate from NOR Gate Implementation of NOT Gate from NOR Gate Implementation of XOR Gate from NOR Gate Implementation of XNOR Gate from NAND Gate Half Adder: Implementation and Truth Table Full Adder: Implementation and Truth Table Half Subtractor: Implementation and Truth Table Implementation of an SR Latch Using NAND Gates Implementation of a 2:1 Multiplexer Using Logic Gates

Karnaugh Map Context 2-Variable Karnaugh Maps 3-Variable Karnaugh Maps and the Wraparound Rule 4-Variable Karnaugh Maps and the Four Corners Don't-Care Conditions Karnaugh Map Worked Examples

Why Circuits Need Memory The SR Latch: Two Gates Remembering a Bit The Gated D Latch: Controlling When Memory Updates The D Flip-Flop: From Level to Edge

Data Structures & Algorithms

Graph Theory Basics for CS

BFS and DFS: Walking a Graph Shortest Paths with Dijkstra Minimum Spanning Trees: Kruskal and Prim

Topological Sort and Cycle Detection Strongly Connected Components with Tarjan Bellman-Ford: Shortest Paths with Negative Weights

Introduction to Backtracking Subsets and Combination Sum Permutations of a String The N-Queens Problem Palindrome Partitioning Graph M-Coloring Sudoku: Where Plain Backtracking Runs Out

Introduction to Sorting Merge Sort, Step by Step Quick Sort, Step by Step Heap Sort and Sorting Without Comparisons Partition Problems: 0s, 1s and 2s Merge-Based Problems: Union, Intersection and Inversions Interval Problems: Merging and Minimum Platforms Sort, Then One Pass

Two Pointers: Throwing Work Away on Purpose Walking In From Both Ends Read Pointer, Write Pointer Triplets, and Everything Above Them Two Sequences, One Pass Each

Recursion (FULL GUIDE)Memoization and Tabulation Two Axes: Reading the Answer Back Out Take It or Leave It: the Knapsack

Longest Increasing Subsequence in O(n log n)Sliding Window Maximum with a Monotonic Deque Edit Distance: the Levenshtein Table, Row by Row Median of Two Sorted Arrays in O(log(min(n, m)))

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Tutorials/Digital Logic

Digital Logic

Gates, boolean simplification and memory, built from the ground up. Start with a single NAND gate and end up with circuits that remember.

25 lessons across 3 sections

Start with Implementation of AND Gate from NAND Gate →

Gate & Circuit Implementations

1Implementation of AND Gate from NAND Gate→
2Implementation of OR Gate from NAND Gate→
3Implementation of NOT Gate from NAND Gate→
4Implementation of XOR Gate from NAND Gate→
5Implementation of NOR Gate from NAND Gate→
6Implementation of AND Gate from NOR Gate→
7Implementation of OR Gate from NOR Gate→
8Implementation of NOT Gate from NOR Gate→
9Implementation of XOR Gate from NOR Gate→
10Implementation of XNOR Gate from NAND Gate→
11Half Adder: Implementation and Truth Table→
12Full Adder: Implementation and Truth Table→
13Half Subtractor: Implementation and Truth Table→
14Implementation of an SR Latch Using NAND Gates→
15Implementation of a 2:1 Multiplexer Using Logic Gates→

Intro To Karnaugh Maps

1Karnaugh Map Context→
22-Variable Karnaugh Maps→
33-Variable Karnaugh Maps and the Wraparound Rule→
44-Variable Karnaugh Maps and the Four Corners→
5Don't-Care Conditions→
6Karnaugh Map Worked Examples→

Understanding Sequential Logic

1Why Circuits Need Memory→
2The SR Latch: Two Gates Remembering a Bit→
3The Gated D Latch: Controlling When Memory Updates→
4The D Flip-Flop: From Level to Edge→