The D Flip-Flop: From Level to Edge

From the outside, a D flip-flop looks almost identical to the gated D latch, with one data input D, one clock input CLK, and outputs Q and NOT-Q. The behavior inside is completely different. That difference is exactly the fix the previous tutorial promised.

Level-Sensitive vs. Edge-Sensitive

A level-sensitive latch cares about a signal's value over a stretch of time, while E is high. An edge-sensitive flip-flop cares instead about a signal's transition at one specific moment, the rising edge where CLK goes from 0 to 1, and it is blind to D the rest of the time. Every other instant, Q simply holds.

Built From Two Latches: Master and Slave

The circuit below is wired the way real hardware builds one: two gated D latches in series, a master and a slave, with the master's enable wired to CLK inverted and the slave's enable wired to CLK directly. Fifteen gates total, and every one is a NAND or a NOT you already know.

CLK = 0:  master enable = 1 (transparent), slave enable = 0 (holding)
            master follows D, slave holds its last value

CLK = 1:  master enable = 0 (holding), slave enable = 1 (transparent)
            master freezes whatever D was an instant before CLK rose,
            slave immediately copies that frozen value out to Q

The two enables are inverted copies of each other, so they can never both be transparent at once. That is what turns two level-sensitive latches into one edge-sensitive flip-flop. At every instant exactly one of the two is open. D can only reach Q by passing through both, master then slave, and that only happens in the narrow window right as CLK transitions from low to high.

Try It: Sampling Once Per Tick

Toggle D as many times as you like while CLK stays put. Nothing happens to Q, because nothing you are touching is a clock edge. Now toggle CLK from 0 to 1 and back, and watch the master latch freeze the instant CLK rises, right as the slave latch opens and copies whatever the master was holding out to Q. That handoff is the entire mechanism.

Why Registers Use Flip-Flops, Not Latches

Chain several D flip-flops together, output of one into the input of the next, all sharing a single clock line, and you get the building block a shift register or a counter is made of. Every flip-flop samples at the exact same instant, so each stage advances by exactly one step per clock tick. No stage can race ahead into the next one mid-cycle. For all but that one instant, every flip-flop in the chain is simply holding.

That guarantee is the entire reason edge-triggered storage exists. A multi-stage design built from plain gated latches would need careful, error-prone timing analysis to avoid race-through on every chain of them, exactly the problem raised at the end of the last tutorial.

How the Simulator Actually Implements This

Worth calling out directly: the underlying simulation engine does not give a flip-flop any special memory-cell data structure. Even the built-in primitive version does what this gate-level circuit does by construction. A flip-flop's Q output is just an ordinary output pin. The engine's runtime state already tracks what every pin is currently driving, so the stored bit is that pin's drive state and nothing more. Detecting the rising edge works by comparing a net's value immediately before and after it resolves during the same simulation step, a comparison the engine already computes for every net that changed.

The Full Arc, In One Line Each

1. A feedback loop turns two ordinary gates into an SR latch.
2. Gating logic (D, E) turns the SR latch into a gated D latch, no forbidden state.
3. Two gated D latches with inverted enables turn that into a D flip-flop, edge-triggered.
4. A D flip-flop, wired up N times, is an N-bit register.

Nothing above a plain logic gate was ever required to get here.