The Gated D Latch: Controlling When Memory Updates

The SR latch has a forbidden state because it hands you two levers, S and R, and trusts you never to pull both at once. The gated D latch fixes that. It removes the second lever entirely, so there is only one input to set and nothing left for it to contradict.

One Data Input Instead of Two

There is one data input, D, plus a second input, E, for enable. With only one data value in play, no combination of inputs can mean two contradictory things at once, which is a stronger guarantee than it first sounds. The forbidden state is not handled better here, it simply has no way to occur, since building it would require two conflicting values at once and there is only ever the one.

How D and E Become S and R

Under the hood it is still an SR latch. One NOT gate and two extra NAND gates sit in front of the same cross-coupled NAND pair, deriving S and R from D and E. D feeds one gate directly and its inverse feeds the other. So the two derived signals can never both demand the forbidden combination, and they either disagree, which is an update, or go inactive together, which is a hold.

S = NAND(D, E)
R = NAND(NOT(D), E)

E = 0:  S = 1, R = 1  ->  SR latch holds (both NAND outputs forced high, no change)
E = 1:  S = NOT(D), R = D  ->  D drives Q directly through the latch

This can look like a new kind of primitive, but it is really just a disciplined way of driving the one you already have, wired so that the bad combination is never reachable in the first place.

Transparent vs. Holding

The whole behavior reduces to one rule. While E is high, Q follows D immediately, and the latch is called transparent because it is not storing anything yet, it is letting D pass straight through to Q. The instant E drops low, whatever Q was showing freezes. D can then wiggle freely with no effect on Q until E goes high again.

Try both halves of that rule below. With E off, click D a few times and confirm Q never moves, because the signal dies partway through the gating logic instead of reaching the latch. Then turn E on and click D again. Q tracks it instantly, through the five real gates that make it happen.

Still Level-Sensitive

The gated D latch solves the forbidden-state problem. It keeps one property from the SR latch that matters enormously once you chain these together: it reacts to a level, not to a moment. Transparent while E is high means transparent for the entire stretch of time E happens to be high, which could span many gate delays.

Why That's a Problem: Race-Through

Chain them the way a shift register needs to, with latch A feeding latch B and both sharing one enable. Now the trouble starts. While that enable is high, a change can ripple straight through A into B before E has any chance to drop, so data races through several stages in a single tick instead of moving one stage at a time. Engineers call this race-through.

The Fix: React to a Moment, Not a Level

What registers and counters need is a storage element that ignores D almost all the time. It should sample D at one precise, vanishingly brief instant per clock cycle, so that chaining stage after stage moves data forward by exactly one step per tick. That is a D flip-flop. It is built from two of this exact gated D latch, not from a new kind of gate.